Qynetic Labs · In prototype
The maker’s AI board. Built in India.
In design since December 2024 · ~0.8 TOPS NPU · Designed in India
Scroll, and we’ll take you around Vayu One, part by part.
Fig. 1 Vayu One · interactive 3D model of the design
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A compact AI computer with an on-chip NPU, designed end to end in KiCad by our team in Tamil Nadu since December 2024.
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Four Arm Cortex-A55 cores and an NPU for about 0.8 TOPS of on-device inference, in a 636-ball BGA package at the centre of the board.
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Low-power memory placed right beside the SoC, so the high-speed traces between them stay short.
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The RK809 power-management IC and its buck regulators turn one USB-C input into every rail the board needs.
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HDMI out, two USB 3.0 ports through a VIA VL817 hub, and Gigabit Ethernet on a Realtek PHY.
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USB-C Power Delivery for input, and a microSD slot for the operating system and your data.
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GPIO with a Raspberry-Pi-compatible pinout, for the sensors and add-ons you already have.
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A MIPI-CSI camera connector feeds frames straight to the NPU for detection, segmentation and OCR.
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A Wi-Fi 6 and Bluetooth module sits on the underside, next to a coin-cell holder for the real-time clock.
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QyneticOS and QyneticRT run on Vayu One exactly as they do on every larger Vayu board.
An NPU on board. About 0.8 TOPS for on-device detection, segmentation and OCR, on a Rockchip RK3568.
Desktop-class I/O. HDMI out, two USB 3.0 ports and Gigabit Ethernet, with Wi-Fi 6 and Bluetooth built in.
A familiar 40-pin header. A Raspberry-Pi-compatible pinout for the sensors and add-ons you already have.
Ready for vision. A MIPI-CSI camera connector feeds frames straight to the NPU.
Wireless, underneath. The Wi-Fi 6 and Bluetooth module sits on the underside, next to a battery-backed real-time clock.
import qrt
# the same two lines on every Vayu board
qrt.run("yolov8n.onnx", source="camera:0")One runtime. Every model. ONNX, TFLite, PyTorch and GGUF through one API, the same on every Vayu board.
The header follows the Raspberry Pi pinout, pin for pin. Pick a pin or a bus to see what it does and where it lands on the RK3568.
Everything on the board.
0.8 → 434 TOPS
RISC-V NPU · roadmap
Qynetic Labs Private Limited/Chennai, India
Qynetic Labs (QyneticLabs) designs affordable Vayu edge AI computers in India, with QyneticOS, the QyneticRT runtime and a roadmap to our own QChip silicon.
00Why Qynetic
High-end edge AI in India is imported, expensive and supported from far away. The cloud adds latency, recurring cost and hard questions about where data lives. We think the compute that runs India’s AI should be designed here, priced here and supported here.
Edge-AI boards such as NVIDIA Jetson are expensive and supply-constrained, which puts them out of reach for many Indian developers, startups, institutions and OEMs.
Latency, recurring cost and data-sovereignty concerns rule the cloud out for many industrial, civic and defence deployments.
Few rupee-priced, full-stack options, little India-local support, and no GeM-friendly domestic supply.
40–60%
The premium typically paid for imported edge-AI hardware, compared with an India-built full stack. That gap is what we’re here to close.
01Platform
Five layers that reinforce each other. Because every layer is ours, a model built on one Vayu board runs on all of them, and it’s tuned end to end.
Single-board computers that pair capable NPUs with dedicated AI accelerators on the higher tiers. Five boards, one family: from a Raspberry-Pi-compatible maker board to an industrial DIN-rail unit.
Ready
Ubuntu 24.04 LTS on the Rockchip 6.1 kernel, with every accelerator driver pre-installed, A/B boot through U-Boot and over-the-air updates. Reproducible builds: every commit produces a flashable image.
The core of the platform: one runtime that detects the accelerator on the board and runs ONNX, TFLite, PyTorch and GGUF models through a single API. Nothing vendor-specific to learn.
Camera-to-inference pipelines for detection, segmentation, pose and OCR, and ROS 2 perception nodes for robots and drones, with a pre-optimised model zoo.
Fleet management, telemetry and over-the-air updates for every device, with an on-premise, air-gapped mode for defence, railways and other secure deployments.
02The Vayu family
Start on a maker board and scale to a 434-TOPS vision powerhouse without rewriting a line. Drag along the scale, or pick a board.
Entry · Maker
0.8 TOPS NPU
The Raspberry-Pi-sized way in.
Three questions. We’ll point you to a board.
| Board | Tier | AI compute | Form factor | Status |
|---|---|---|---|---|
| Vayu One | Entry · Maker | ~0.8 TOPS | 100 × 70 mm | Designed · prototyping |
| Vayu Neo | Mid-range | 6 TOPS + M.2 AI | 100 × 72 mm | Planned |
| Vayu Pro | Performance | 32–58 TOPS | 120 × 90 mm | Planned |
| Vayu Ultra | Flagship | 220–434 TOPS | 150 × 100 mm | In development |
| Vayu Axis | Industrial | up to 58 TOPS | DIN rail | Planned |
03QyneticRT
QyneticRT finds the accelerator on whichever Vayu board it lands on and sends your model there. One API, no vendor toolchains, and room to grow: plug in an accelerator and the same code uses it.
Pre-optimised model zoo
detect.py
import qrt
# the same two lines on every Vayu board
qrt.run("yolov8n.onnx", source="camera:0")04Why teams choose Qynetic
−40–60%
Designed to cost 40–60% less than comparable imported edge-AI hardware, through a lean bill of materials and India-based manufacturing.
GeM
Rupee invoicing and a domestic supply path designed for government, PSU and institutional buyers.
IST
India-local support and service from the people who designed the board.
On-prem
On-premise fleet management for defence, railways and other deployments where data can’t leave the building.
OEM
Evaluation boards, custom board variants and design-ins for product companies and integrators, then volume supply.
Open
Linux, ONNX and ROS 2 underneath, so your models and code stay portable.
05QChip
Every board we ship funds the chip. QChip brings the AI accelerator in-house: an India-designed RISC-V NPU that makes the platform cost-independent and builds India-owned semiconductor IP.
Generation 1 · architecture & FPGA prototype
40–80 TOPS
RISC-V CPU and a vector NPU on a 28 nm process.
06Applications
Wherever a camera, a sensor or a robot needs an answer in milliseconds, without sending data away to get it.
Detection, segmentation and OCR on live camera feeds.
ROS 2 perception on board, with no round trip to the cloud.
Defect inspection and predictive maintenance on the line.
Traffic and safety analytics right where the cameras are.
Footfall and shelf analytics without shipping video off-site.
Crop and pest detection at the farm edge.
Air-gapped, domestically sourced AI compute.
On-premise inference that keeps patient data in the building.
07Progress
Vayu One has been in design since December 2024. Qynetic Labs was incorporated in June 2026 to take it to market. Here’s what is done, what we’re working on now, and the 18-month plan that follows.
Dec 2024
Before there was a company, Trijal starts designing Vayu One in KiCad: the RK3568 SoC, its memory and its power tree.
18 Jun 2026
Qynetic Labs Private Limited, under the Companies Act, 2013. CIN U26107TN2026PTC194272.
26 Jun 2026
Udyam registration UDYAM-TN-24-0183917, as a manufacturing enterprise.
2026
RK3568 (636-ball BGA), dual-channel LPDDR4X, RK809 PMIC, Gigabit Ethernet, USB-C PD and an impedance-controlled stackup, with a verified design spec and preliminary fabrication package.
2026
The five-board lineup, the QyneticOS and QyneticRT architecture, and the QChip silicon plan.
Oct 2026
Ubuntu 24.04 LTS on the Rockchip 6.1 kernel with NPU drivers, A/B boot with U-Boot, and over-the-air updates.
Now
A System-on-Module path puts the riskiest engineering (SoC, memory, power) on a proven module, for a fast, reliable route to working hardware.
Now
Our flagship: a 220–434 TOPS vision server you can hold, with one or two high-performance AI accelerators.
Months 0–4
Board, power, interfaces and drivers.
Months 4–9
Accelerator integration and the model zoo, on QyneticOS.
Months 9–13
Benchmarking and pilot deployments with early users.
Months 13–18
Documentation, BIS / FCC / CE certification readiness, and scale-up.
08Team
Founder & CEO · Hardware lead
Has been designing Vayu One since December 2024, end to end in KiCad: BGA SoC integration, LPDDR4X routing, the PMIC power tree and an impedance-controlled stackup. Drives product, hardware and company strategy. B.E. Computer Science (Cyber Security).
Co-Director · Operations & governance
Founding director. Leads corporate affairs, operations and compliance.
Building the core team
We’re looking for hardware, embedded-Linux and ML-runtime engineers who want to build India’s AI compute from the board up.
Every detail below can be checked on a government portal.
MCA
18 June 2026
CIN U26107TN2026PTC194272
A private company limited by shares, under the Companies Act, 2013.
Verify on MCAMSME
Micro enterprise
UDYAM-TN-24-0183917
Registered as a manufacturing enterprise with the Ministry of MSME on 26 June 2026.
Verify on UdyamR&D
December 2024
Vayu One · KiCad · 12-layer
Vayu One was in design for eighteen months before the company was incorporated.
See the timelineHQ
Tamil Nadu, India
Ponneri · Tiruvallur 601204
Directors Trijal P G (DIN 11775560) and Sujatha G (DIN 11775561).
Corporate information09Contact